1. Field of the Invention
The present invention relates to a technique of checking a mask pattern. More particularly, it relates to a method and apparatus for checking a mask pattern formed based on two or more design rules in accordance with functional contents of a semiconductor element.
2. Description of the Related Art
With recent ultra-fine fabrication and increased functions of semiconductor integrated circuit devices, a single mask pattern has included a plurality of mask pattern regions formed based on two or more design pattern rules.
Conventionally, defects in a mask pattern formed based on different design pattern rules have been detected by changing a defect detection reference for each of the mask pattern regions and in turn checking the entire mask pattern repeatedly.
Therefore, where a certain mask pattern region is checked according to a defect detection reference which is not adapted to the mask pattern region, a process must be carried out to discriminate whether a detected defect is a real one or a pseudo one. This causes a problem in that checking takes a long time resulting in a lowering of throughput of the checking apparatus.
In view of the problem, a technique capable of checking a mask pattern efficiently and in a short time has been demanded.